@misc{Jurczak_Małgorzata_Challenges,
 author={Jurczak, Małgorzata and Rotschild, Aude and Severi, Simone and Keersgieter de, An and Henson, Kirklen and Mertens, Sofie and Rooyackers, Rita and Pollentier, Ivan and Scaekers, Marc and Lindsay, Richard and Lauwers, Anne and Augendre, Emmanuel and Veloso, Anabela},
 howpublished={online},
 publisher={Instytut Łączności - Państwowy Instytut Badawczy, Warszawa},
 language={ang},
 title={Challenges in scaling of CMOS devices towards 65 nm node, Journal of Telecommunications and Information Technology, 2005, nr 1},
 type={artykuł},
 keywords={gate stack, device integration, gate patterning, gate dielectrics, silicon recess, silicide, lithography, CMOS devices, shallow junctions},
}