Title:

Challenges in scaling of CMOS devices towards 65 nm node, Journal of Telecommunications and Information Technology, 2005, nr 1

Creator:

Jurczak, Małgorzata ; Rotschild, Aude ; Severi, Simone ; Keersgieter de, An ; Henson, Kirklen ; Mertens, Sofie ; Rooyackers, Rita ; Pollentier, Ivan ; Scaekers, Marc ; Lindsay, Richard ; Lauwers, Anne ; Augendre, Emmanuel ; Veloso, Anabela

Subject and Keywords:

gate stack ; device integration ; gate patterning ; gate dielectrics ; silicon recess ; silicide ; lithography ; CMOS devices ; shallow junctions

Description:

The current trend in scaling transistor gate length below 60 nm is posing great challenges both related to process technology and circuit/system design. From the process technology point of view it is becoming increasingly difficult to continue scaling in traditional way due to fundamental limitations like resolution, quantum effects or random fluctuations. In turn, this has an important impact on electricaldevice specifications especially leakage current and the circuit power dissipation.

Publisher:

Instytut Łączności - Państwowy Instytut Badawczy, Warszawa

Date:

2005, nr 1

Resource Type:

artykuł

Format:

application/pdf

DOI:

10.26636/jtit.2005.1.299

ISSN:

1509-4553

eISSN:

1899-8852

Source:

Journal of Telecommunications and Information Technology

Language:

ang

Rights Management:

Biblioteka Naukowa Instytutu Łączności