Title:

Standardization of the compact model coding: non-fully depleted SOI MOSFET example, Journal of Telecommunications and Information Technology, 2005, nr 1

Creator:

Jakubowski, Andrzej ; Tomaszewski, Daniel ; Grabiński, Władysław ; Lemaitre, Laurent

Subject and Keywords:

SOI MOSFET ; compact model coding ; Verilog-AMS

Description:

The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.

Publisher:

Instytut Łączności - Państwowy Instytut Badawczy, Warszawa

Date:

2005, nr 1

Resource Type:

artykuł

Format:

application/pdf

DOI:

10.26636/jtit.2005.1.278

ISSN:

1509-4553

eISSN:

1899-8852

Source:

Journal of Telecommunications and Information Technology

Language:

ang

Rights Management:

Biblioteka Naukowa Instytutu Łączności