Obiekt

Tytuł: Advanced compact modeling of the deep submicron technologies, Journal of Telecommunications and Information Technology, 2000, nr 3,4

Opis:

The technology of CMOS large-scale integrated circuits (LSI’s) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 mm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model.

Wydawca:

Instytut Łączności - Państwowy Instytut Badawczy, Warszawa

Format:

application/pdf

Identyfikator zasobu:

oai:bc.itl.waw.pl:1641 ; ISSN 1509-4553, on-line: ISSN 1899-8852

DOI:

10.26636/jtit.2000.3-4.29

ISSN:

1509-4553

eISSN:

1899-8852

Źródło:

Journal of Telecommunications and Information Technology

Język:

ang

Prawa:

Biblioteka Naukowa Instytutu Łączności

Kolekcje, do których przypisany jest obiekt:

Data ostatniej modyfikacji:

16 maj 2024

Data dodania obiektu:

20 maj 2014

Liczba wyświetleń treści obiektu:

149

Wszystkie dostępne wersje tego obiektu:

https://bc.itl.waw.pl/publication/1841

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