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Title: Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model, Journal of Telecommunications and Information Technology, 2009, nr 4

Creator:

Yumisaki, Akihiro ; Sadachika, Norio ; Mattausch, Hans Jurgen ; Miura-Mattausch, Mitiko ; Koide, Tetsushi ; Johguchi, Koh ; Kaya, Akihiro

Date:

2009, nr 4

Resource Type:

artykuł

Description:

An analysis of the measured macroscopic withinwafer variations for threshold voltage (Vth) and on-current (Ion) over several technology generations (180 nm, 100 nm and 65 nm) is reported. It is verified that the dominant microscopic variations of the MOSFET device can be extracted quantitatively from these macroscopic variation data by applying the surface-potential compact model Hiroshima University STARC IGFET model 2 (HiSIM2), which is presently brought into industrial application. Only a small number of microscopic parameters, representing substrate doping (NSUBC), pocket-implantation doping (NSUBP), carrier-mobility degradation due to gate-interface roughness (MUESR1) and channel-length variation during the gate formation (XLD) are found sufficient to quantitatively reproduce the measured macroscopic within-wafer variations of Vth and Ion for all channel length Lg and all technology generations. Quantitative improvements from 180 nm to 65 nm are confirmed to be quite large for MUESR1 (about 70%) and Lmin(XLD) (55%) variations, related to the gate-oxide interface and the gate-stack structuring, respectively. On the other hand, doping-related technology advances, which are reflected by the variation magnitudes of NSUBC (30%) and NSUBP (25%), are found to be considerably smaller. Furthermore, specific combinations of extreme microscopic parameter-variation values are able to represent the boundaries of macroscopic fabrication inaccuracies for Vth and Ion. These combinations are found to remain identical, not only for all Lg of a given technology node, but also for all investigated technologies with minimum Lg of 180 nm, 100 nm and 65 nm.

Publisher:

Instytut Łączności - Państwowy Instytut Badawczy, Warszawa

Format:

application/pdf

Resource Identifier:

oai:bc.itl.waw.pl:471 ; ISSN 1509-4553, on-line: ISSN 1899-8852

DOI:

10.26636/jtit.2009.4.959

ISSN:

1509-4553

eISSN:

1899-8852

Source:

Journal of Telecommunications and Information Technology

Language:

ang

Rights Management:

Biblioteka Naukowa Instytutu Łączności

Subject and keywords:

silicon potential at channel surface microscopic macroscopic within wafer field-effect transistor fabrication inaccuracy compact model

Object collections:

Last modified:

Aug 27, 2024

In our library since:

Mar 8, 2010

Number of object content hits:

634

All available object's versions:

https://bc.itl.waw.pl/publication/529

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Edition name Date
Mattausch, Hans Jurgen; Yumisaki, Akihiro; Sadachika, Norio; Kaya, Akihiro; Johguchi, Koh; Koide, Tetsushi; Miura-Mattausch, Mitiko, Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model, Journal of Telecommunications and Information Technology, 2009, nr 4 Aug 27, 2024

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