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Title: Challenges for 10 nm MOSFET process integration, Journal of Telecommunications and Information Technology, 2007, nr 2

Creator:

Hellström, Per-Erik ; Haartman von, Martin ; Östling, Mikael ; Zhang, Zhen ; Hallstedt, Julius ; Zhang, Shili ; Malm, Bengt Gunnar

Date:

2007, nr 2

Resource Type:

artykuł

Description:

An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.

Publisher:

Instytut Łączności - Państwowy Instytut Badawczy, Warszawa

Format:

application/pdf

Resource Identifier:

oai:bc.itl.waw.pl:249

DOI:

10.26636/jtit.2007.2.805

ISSN:

1509-4553

eISSN:

1899-8852

Source:

Journal of Telecommunications and Information Technology

Language:

ang

Rights Management:

Biblioteka Naukowa Instytutu Łączności

Subject and keywords:

sstrained silicon silicon germanium hafnium oxide high-k dielectrics mobility low-frequency noise nano-wire silicon-on-insulator (SOI) metal gate

Object collections:

Last modified:

Feb 25, 2026

In our library since:

Jan 8, 2010

Number of object content hits:

205

All available object's versions:

https://bc.itl.waw.pl/publication/284

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Edition name Date
Östling, Mikael; Malm, Bengt Gunnar; Haartman von, Martin; Hallstedt, Julius; Zhang, Zhen; Hellström, Per-Erik; Zhang, Shili, Challenges for 10 nm MOSFET process integration, Journal of Telecommunications and Information Technology, 2007, nr 2 Feb 25, 2026

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