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Pleskacz, Witold A. ; Rakowski, Michał
2007, nr 3
artykuł
This paper describes the analysis of the influence of yield loss model parameters on the calculation of the probability of arising shorts between conducting paths in IC’s. The characterization of the standard cell in AMS 0.8 μm CMOS technology is presented as well as obtained probability results and estimations of yield loss by changing values of model parameters.
Instytut Łączności - Państwowy Instytut Badawczy, Warszawa
application/pdf
oai:bc.itl.waw.pl:296
10.26636/jtit.2007.3.840
1509-4553
1899-8852
Journal of Telecommunications and Information Technology
ang
Biblioteka Naukowa Instytutu Łączności
Jul 24, 2024
Jan 28, 2010
220
https://bc.itl.waw.pl/publication/339
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OAI-PMH
Citation style: Chicago ISO690
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